CSS Computer Science MCQs

PPSC FPSC KPPSC BPSC SPSC Lecturer Computer Science Test 53

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There will be 25 multiple choice question in the test.
Answer of the questions will change randomly each time you start this test.
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Test Instructions:-
Test Name	Lecturer Computer Science
Subject	Computer Science Test 53
Test Type	MCQs
Total Questions	25
Total Time	20 Minutes
Total Marks	100

You have 20 minutes to pass to the quiz.

Lecturer Computer Science Online Test No. 53

1 / 25

The following is not true for master/slave architecture:

A failure of master brings down the whole system

Operating system kernel runs on master processor only.

Operating system kernel can run on any processor either master or slave.

All scheduling and process management is done on master processor.

2 / 25

The principal function of a process is:

To execute machine instructions residing in main memory.

To execute assembly instructions residing outside main memory.

A and B both true.

A and B both false.

3 / 25

process control blocks are referred for:

Process control

I/O devices

Memory allocation

None of these.

4 / 25

OS/390 is a:

Single user system

Multi user system

Single tasking system

None of these.

5 / 25

Multithreading allows:

To run threads concurrently

To run threads independently

A is true, B is false

A and B both true.

6 / 25

The two state process models have the following states:

Running and Not Running

Running and Ready

Ready and Blocked

New and Ready.

7 / 25

The concept used to support multi programming environment on a computer is:

Virtual memory

Hierarchy of physical memory

Display of multiple windows

None the above.

8 / 25

The OS/2 is the operating system that support:

Single thread per process

Multiple thread per process

Single process

None of these.

9 / 25

Operating System is:

Software

Hardware

Software and Hardware both

None of these.

10 / 25

Window 98 is a:

Single user system

Multi user system

Single tasking system

None of these.

11 / 25

For multithreading:

Tasks to be performed can be independent

Task to be performed is essentially serialized.

Tasks cannot be divided into number of threads.

None is true.

12 / 25

The cluster is a case of:

Distributed memory

Shared memory

Master/slave architecture

Symmetric multi processor.

13 / 25

Process control block is also referred as:

Fast control block

Process descriptor

Task descriptor

A, B, C are all true.

14 / 25

The master/slave architecture is an example of:

Distributed memory processing

Shared memory processing

Symmetric multi processing

None of these.

15 / 25

The trace of the process is:

A set of instructions that execute process

A listing of sequence of instructions that execute process

A track of network

None of these.

16 / 25

The operating system control tables maintain process tables, because:

These tables manages I/O devices

These tables manages files

These tables manages memory

None of these.

17 / 25

Instruction processing consists of:

Fetch cycle only

Execution cycle only

Fetch and Execution cycle both

None of these.

18 / 25

With trap in process control:

Operating system determines the error or exception condition that is fatal.

Operating system interrupted for maximum allowable time.

Are tables that manage information process

None of these.

19 / 25

The only state transition initiated by the user process itself in an operating system is

Block

Dispatch

Wake up

20 / 25

Windows XP is:

Uni-programming processes

Multi programming processes

Hardware

None of these.

21 / 25

I/O modules in computer:

Controls the operation of the computer.

Stores data and program.

Move data between the computer and external environment.

Provides communication among processors and main memory.

22 / 25

In shared memory multi processor:

Computer communicate to each other by fixed paths

Computer communicates to each other via a shared memory.

Each processing element is a self contained computer.

None of these.

23 / 25

The following:

Start? Fetch next instruction? Execute Instruction ? Halt, represents

Instruction cycle with interrupt

Instruction cycle without interrupt

Instruction cycle with two interrupts

None of these

24 / 25

Thread is:

Dispatch able unit of work

Can be interrupted

A and B both true

A and B both false.

25 / 25

Instruction register contains:

The address of an instruction to be fetched.

The instructions most recently fetched.

The data to be written into memory.

The data to be read from memory.

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The average score is 0%

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